Datasheet

Figure 32-31. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1
SSIClk
(SPO=0)
SSITx
(to slave)
SSIRx
( from slave)
SSIClk
(SPO=1)
S2
S1
S5
SSIFss
LSB
S3
S8
S6
S7
S9
MSB
S4
LSBMSB
Figure 32-32. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1
SSIClk
(SPO=0)
SSITx
(to master)
SSIRx
( from master)
SSIClk
(SPO=1)
S2
S1
S5
SSIFss
LSB
S3
S12
S10
S11
S13
MSB
S4
LSBMSB
S3
Table 32-47. Bi- and Quad-SSI Characteristics
UnitMaxNomMinParameter NameParameterParameter No.
ns--16.67SSIClk cycle time, as master
a
T
CLK_PER
S15
ns--8.33SSIClk high time, as masterT
CLK_HIGH
S16
ns--8.33SSIClk low time, as masterT
CLK_LOW
S17
ns--1.25SSIClk rise time
c
T
CLKR
S18
December 13, 20132144
Texas Instruments-Advance Information
Electrical Characteristics