Datasheet

Table 32-44. ADC Electrical Characteristics for ADC at 1 Msps (continued)
UnitMaxNomMinParameter NameParameter
dB-6560Signal-to-noise-ratio, Single-ended input, V
ADCIN
:
-20dB FS, 1KHz
y
SNR
S
dB-7270Signal-to-distortion ratio, Single-ended input,
V
ADCIN
: -3dB FS, 1KHz
uv
SDR
S
dB-6360Signal-to-Noise+Distortion ratio, Single-ended
input, V
ADCIN
: -3dB FS, 1KHz
ywx
SNDR
S
TEMPERATURE SENSOR
V-1.633-Temperature sensor voltage, junction
temperature 25 °C
V
TSENS
mV/°C--13.3-Temperature sensor slope at:
-40°C to 85 °C ambient (industrial temperature
part)
-40°C to 105 °C ambient (extended temperature
part)
S
TSENS
°C±5--Temperature sensor accuracy at:
-40°C to 85 °C ambient (industrial temperature
part)
-40°C to 105 °C ambient (extended temperature
part)
z
E
TSENS
a. Values are at V
REF+
= 3.3V, F
ADC
=16 MHz unless otherwise noted.
b. Best design practices suggest that static or quiet digital I/O signals be configured adjacent to sensitive analog inputs to
reduce capacitive coupling and cross talk. Unexpected results can occur if a switching digital I/O is placed adjacent to
an ADC input channel or voltage reference input. In addition, analog signals configured adjacent to ADC input channels
or reference inputs must meet the R
ADC
equivalent input resistance given in this table and must be band-limited to 100
kHz or lower.
c. Two capacitors in parallel. Note that these capacitors should be as close to the die as possible.
d. Assumes external filtering network between VREFA+ and VREFA- as shown in Figure 32-28 on page 2142. External reference
noise level must be under 12bit (-74 dB) of Full Scale input, over input bandwidth, measured at VREFA+ - VREFA-.
e. Internal reference is connected directly between V
DDA
and GNDA (VREFi = V
DDA
- GNDA). In this mode, E
O
, E
G
, E
T
, and
dynamic specifications are adversely affected due to internal voltage drop and noise on V
DDA
and GNDA. Internal
reference voltage is selected when VREF field in the ADCCTL register is 0x0.
f. V
ADCIN
= V
INP
- V
INN
g. With signal common mode as V
DDA
/2.
h. With signal common mode as (V
REF+
+ V
REF-)
/2.
i. This parameter is defined as the average of the differential inputs.
j. As shown in Figure 32-29 on page 2142, R
ADC
is the total equivalent resistance in the input line all the way up to the sampling
node at the input of the ADC.
k. See “System Clock Specification with ADC Operation” on page 2122 for full ADC clock frequency specification.
l. ADC conversion time (Tc) includes the ADC sample time (Ts).
m. Low noise environment is assumed in order to obtain values close to spec. Board must have good ground isolation
between analog and digital grounds, a clean reference voltage is assumed, and input signal must be bandlimited to
Nyquist bandwidth. No anti-aliasing filter is provided internally.
n. ADC static measurements taken by averaging over several samples. At least 20-sample averaging is assumed to obtain
expected typical or maximum spec values.
o. 12-bit DNL
p. Gain error is measured at max code after compensating for offset. Gain error is equivalent to "Full Scale Error." It can be
given in % of slope error, or in LSB, as done here.
q. Total Unadjusted Error is the maximum error at any one code versus the ideal ADC curve. It includes all other errors
(offset error, gain error and INL) at any given ADC code.
December 13, 20132138
Texas Instruments-Advance Information
Electrical Characteristics