Datasheet

Table 32-39. EPI SDRAM Characteristics
UnitMaxNomMinConditionParameter NameParameter
ns32-12-mA drive, C
L
= 30 pFEPI Rise Time (from 20% to 80% of
V
DD
)
T
SDRAMR
ns32-12-mA drive, C
L
= 30 pFEPI Fall Time (from 80% to 20% of
V
DD
)
T
SDRAMF
Table 32-40. EPI SDRAM Interface Characteristics
a
UnitMaxNomMinParameter NameParameterParameter No
ns--16.67SDRAM Clock periodT
CK
E1
ns--8.33SDRAM Clock high timeT
CH
E2
ns--8.33SDRAM Clock low timeT
CL
E3
ns4--CLK to output validT
COV
E4
ns4--CLK to output invalidT
COI
E5
ns4--CLK to output tristateT
COT
E6
ns--8.5Input set up to CLKT
S
E7
ns--0CLK to input holdT
H
E8
µs--100Power-up timeT
PU
E9
ns--20Precharge all banksT
RP
E10
ns--66Auto refreshT
RFC
E11
EPI CLK--2Program mode registerT
MRD
E12
a. The EPI SDRAM interface must use 12-mA drive.
Figure 32-18. SDRAM Initialization and Load Mode Register Timing
CLK
(EPI0S31)
CKE
(EPI0S30)
Command
(EPI0S[29:28,19:18])
DQMH, DQML
(EPI0S[17:16])
AD11, AD[9:0]
(EPI0S[11,9:0]
AD10
(EPI0S[10])
BAD[1:0]
(EPI0S[14:13])
AD [15,12]
(EPI0S [15,12])
NOP
PRE
NOP
AREF
NOP
PRE
NOP
AREF
NOP
LOAD
Code
All Banks
Single Bank
Code
Notes:
1. If CS is high at clock high time, all applied commands are NOP.
2. The Mode register may be loaded prior to the auto refresh cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
E9
E10 E11
E12
E1 E2
E3
NOP
AREF
NOP
Active
Row
Row
Bank
December 13, 20132130
Texas Instruments-Advance Information
Electrical Characteristics