Datasheet

32.9.6 System Clock Specification with ADC Operation
Table 32-25. System Clock Characteristics with ADC Operation
UnitMaxNomMinParameter NameParameter
MHz-16-System clock frequency when the ADC module is
operating (when PLL is bypassed).
F
sysadc
32.9.7 System Clock Specification with USB Operation
Table 32-26. System Clock Characteristics with USB Operation
UnitMaxNomMinParameter NameParameter
MHz--30System clock frequency when the USB module is
operating (note that MOSC must be the clock source,
either with or without using the PLL)
F
sysusb
32.10 Sleep Modes
The following tables can be used to calculate the maximum wake time from Sleep or Deep Sleep
depending on the specific application. Depending on the application configuration, each of the
parameters, except for T
FLASH
, add sequential latency to the wake time. Flash restoration happens
in parallel to the other wake processes and its wake time is normally absorbed by the other latencies.
As an example, the wake time for a device in Deep Sleep, with the PIOSC and PLL turned off and
the Flash and SRAM in low power mode is calculated as follows:
Wake Time = T
PIOSCDS
+ T
PLLDS
+ T
SRAMLPDS
T
FLASH
does not contribute to this equation since all other parameters are greater in value.
Note that in Sleep mode the wake time due to a clock source is zero because the device uses the
same clock configuration in Run mode; thus, there is no latency involved with respect to the clocks.
Table 32-27. Wake from Sleep Characteristics
UnitMaxNomMinParameter NameParameterParameter
No
µsN/A
a
--Time to restore PIOSC as System Clock in Sleep
mode
T
PIOSC
D1
µsN/A
b
--Time to restore MOSC as System Clock in Sleep
mode
T
MOSC
D2
µsN/A
c
--Time to restore PLL as System Clock in Sleep modeT
PLL
D3
µs39--Time to restore LDO to 1.2 V in Sleep modeT
LDO
D4
µs5--Time to restore Flash to active state from low power
state in Sleep mode
T
FLASH
D5
µs15--Time to restore SRAM to active state from low
power state in Sleep mode
T
SRAMLP
D6
µs15--Time to restore SRAM to active state from standby
state in Sleep mode
T
SRAMSTBY
D7
a. Because the PIOSC is enabled in both Run and Sleep Mode for this configuration, no restoration time is required.
b. Because the MOSC is enabled in both Run and Sleep Mode for this configuration, no restoration time is required.
c. Because the PLL is enabled in both Run and Sleep Mode for this configuration, no restoration time is required.
December 13, 20132122
Texas Instruments-Advance Information
Electrical Characteristics