Datasheet

32.9.5 Main Oscillator Specifications
Table 32-23. Main Oscillator Input Characteristics
a
UnitMaxNomMinParameter NameParameter
MHz25-4
b
Parallel resonance frequencyF
MOSC
MHz120-0External clock reference (PLL in BYPASS mode)
c
F
REF_XTAL_BYPASS
pF24-12External load capacitance on OSC0, OSC1 pins
d
C
1
, C
2
pF-0.5-Device package stray shunt capacitance
d
C
PKG
pF-0.5-PCB stray shunt capacitance
d
C
PCB
pF4--Total shunt capacitance
d
C
SHUNT
Ω300--Crystal effective series resistance, 4 MHz
e
ESR
Ω200--Crystal effective series resistance, 6 MHz
e
Ω130--Crystal effective series resistance, 8 MHz
e
Ω120--Crystal effective series resistance, 12 MHz
e
Ω100--Crystal effective series resistance, 16 MHz
e
Ω50--Crystal effective series resistance, 25 MHz
e
mW-OSC
PWR
-Oscillator output drive level
f
DL
ms18--Oscillator startup time, when using a crystal
g
T
START
VV
DD
-0.65 * V
DD
CMOS input high level, when using an external
oscillator
V
IH
V0.35 * V
DD
-GNDCMOS input low level, when using an external
oscillator
V
IL
mV--150CMOS input buffer hysteresis, when using an external
oscillator
V
HYS
%55-45External clock reference duty cycleDC
OSC_EXT
a. Refer to Table 32-50 on page 2146 and Table 32-51 on page 2147 for additional Ethernet crystal requirements.
b. 5 MHz is the minimum when using the PLL.
c. Pending characterization
d. See information below table.
e. Crystal ESR specified by crystal manufacturer.
f. OSC
PWR
= (2 * pi * F
P
* C
L
* 2.5)
2
* ESR / 2. An estimation of the typical power delivered to the crystal is based on the C
L
,
F
P
and ESR parameters of the crystal in the circuit as calculated by the OSC
PWR
equation. Ensure that the value
calculated for OSC
PWR
does not exceed the crystal's drive-level maximum.
g. Oscillator startup time is specified from the time the oscillator is enabled to when it reaches a stable point of oscillation
such that the internal clock is valid.
The load capacitors added on the board, C
1
and C
2
, should be chosen such that the following
equation is satisfied (see Table 32-23 on page 2119 for typical values and Table 32-24 on page 2120
for detailed crystal parameter information).
■ C
L
= load capacitance specified by crystal manufacturer
■ C
L
= (C
1
*C
2
)/(C
1
+C
2
) + C
SHUNT
■ C
SHUNT
= C
0
+ C
PKG
+ C
PCB
(total shunt capacitance seen across OSC0, OSC1 crystal inputs)
■ C
PKG
, C
PCB
= the mutual caps as measured across the OSC0,OSC1 pins excluding the crystal.
■ C
0
= Shunt capacitance of crystal specified by the crystal manufacturer
2119December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller