Datasheet

Figure 32-8. POR-BOR V
DD
Droop Response
32.7 Reset
Table 32-14. Reset Characteristics
a
UnitMaxNomMinParameter NameParameterParameter
No.
µs126-0.44Digital POR to Internal Reset assertion
delay
c
T
DPORDLY
b
R1
ms-7-Internal Reset timeoutT
IRTOUT
b
R2
µs125-0.44BOR0 to Internal Reset assertion delay
c
T
BOR0DLY
b
R3
µs-0.25
d
/100
e
-Minimum RST pulse widthT
RSTMIN
R4
µs-0.85-RST to Internal Reset assertion delayT
IRHWDLY
R5
µs-2.44-Internal reset timeout after
software-initiated system reset
T
IRSWR
b
R6
µs-2.44-Internal reset timeout after Watchdog resetT
IRWDR
b
R7
µs-2.44-Internal reset timeout after MOSC failure
reset
T
IRMFR
b
R8
a. Minimum timings are for reset assertion using PIOSC as a clock source. Maximum timings are for reset assertion using
LFIOSC in Deep-Sleep Operation.
b. These values are based on simulation.
c. Timing values are dependent on the V
DD
power-down ramp rate.
d. Standard operation.
e. Deep-sleep operation with PIOSC powered down.
December 13, 20132112
Texas Instruments-Advance Information
Electrical Characteristics