Datasheet

Figure 32-2. JTAG Test Clock Input Timing
TCK
J6 J5
J3 J4
J2
Figure 32-3. JTAG Test Access Port (TAP) Timing
TDO Output Valid
TCK
TDO Output Valid
J12
TDO
TDI
TMS
TDI Input Valid TDI Input Valid
J13
J9 J10
TMS Input Valid
J9 J10
TMS Input Valid
J11
J7 J8J8J7
32.6 Power and Brown-Out
Table 32-13. Power and Brown-Out Levels
a
UnitMaxNomMinParameter NameParameterParameter
No.
µs∞--Analog Supply voltage (V
DDA
) rise timeT
VDDA_RISE
P1
µs∞--I/O Supply voltage (V
DD
) rise timeT
VDD_RISE
P2
µs150-10Core Supply Voltage (V
DDC
) rise timeT
VDDC_RISE
b
P3
V2.552.302.00Power-On Reset ThresholdV
POR
P4
V2.972.822.67V
DDA
Power-OK Threshold (Rising Edge)V
DDA_POK
P5
V2.892.802.71V
DDA
Brown-Out Reset ThresholdV
DDA_BOR0
P6
V2.902.802.65V
DD
Power-OK Threshold (Rising Edge)
V
DD_POK
P7
V2.852.762.67V
DD
Power-OK Threshold (Falling Edge)
V2.952.862.77V
DD
Brown-Out Reset ThresholdV
DD_BOR0
P8
V1.100.950.85V
DDC
Power-OK Threshold (Rising Edge)
V
DDC_POK
P9
V0.850.800.71V
DDC
Power-OK Threshold (Falling Edge)
a. All values in this table are based on simulation and are pending characterization.
b. The MIN and MAX values are based on an external filter capacitor load within the range of C
LDO
. Please refer to “On-Chip
Low Drop-Out (LDO) Regulator” on page 2114 for the C
LDO
value.
2107December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller