Datasheet

Table 31-7. Connections for Unused Signals (212-Ball BGA) (continued)
Preferred PracticeAcceptable PracticePin NumberSignal NameFunction
GNDGNDR18GNDX
Hibernate
NCNCM17HIB
VDDNCP19VBAT
GNDNCU18WAKE
GNDNCT18XOSC0
NCNCT19XOSC1
NCNCSee NC pin numbers in
Table 31-3 on page 2054
NCNo
Connects
GNDGNDD18GNDX2
System
Control
GNDNCE19OSC0
NCNCD19OSC1
Pull up as shown in Figure
5-1 on page 234
VDDP18RST
Pull-down to GND with 1K
resistor
d
NCB18USB0DM / PL7
USB
Pull-down to GND with 1K
resistor
d
NCC18USB0DP /PL6
a. The internal Ethernet PHY should not be enabled when RBIAS is not connected. The ROM boot loader will enable the
internal Ethernet PHY if no code is present in the flash and a 24-25 Mhz crystal is attached to the OSC0/OSC1 pins.
b. PA1 (UART0TX) may be enabled as an output by the ROM boot loader if no code is present in the flash and PA0 (UART0RX)
receives a valid boot signature. Ensure that this condition will not occur if PA1 is to be connected directly to GND.
c. PA4 (SSI0XDAT0) may be enabled as an output by the ROM boot loader if no code is present in the flash and the SSI0X
(PA2, PA3, PA5) receives a valid boot signature. Ensure that this condition will not occur if PA4 is to be connected
directly to GND.
d. The ROM boot loader may configure these pins as USB pins if no code is present in the flash therefore they should not
be directly connected to ground.
December 13, 20132100
Texas Instruments-Advance Information
Signal Tables