Datasheet
Table 5-18. Module Power Control ........................................................................................ 478
Table 5-19. Module Power Control ........................................................................................ 484
Table 5-20. Module Power Control ........................................................................................ 486
Table 5-21. Module Power Control ........................................................................................ 488
Table 5-22. Module Power Control ........................................................................................ 490
Table 5-23. Module Power Control ........................................................................................ 493
Table 5-24. Module Power Control ........................................................................................ 495
Table 5-25. Module Power Control ........................................................................................ 499
Table 5-26. Module Power Control ........................................................................................ 501
Table 5-27. Module Power Control ........................................................................................ 503
Table 5-28. Module Power Control ........................................................................................ 505
Table 5-29. Module Power Control ........................................................................................ 507
Table 5-30. Module Power Control ........................................................................................ 509
Table 5-31. Module Power Control ........................................................................................ 511
Table 5-32. Module Power Control ........................................................................................ 513
Table 5-33. Module Power Control ........................................................................................ 515
Table 5-34. Module Power Control ........................................................................................ 517
Table 5-35. Module Power Control ........................................................................................ 519
Table 5-36. Module Power Control ........................................................................................ 521
Table 6-1. System Exception Register Map ......................................................................... 553
Table 7-1. Hibernate Signals (212BGA) .............................................................................. 564
Table 7-2. HIB Clock Source Configurations ........................................................................ 566
Table 7-3. Hibernation Module Register Map ....................................................................... 582
Table 8-1. MEMTIM0 Register Configuration versus Frequency ............................................ 635
Table 8-2. Flash Memory Protection Policy Combinations .................................................... 640
Table 8-3. User-Programmable Flash Memory Resident Registers ....................................... 644
Table 8-4. MEMTIM0 Register Configuration versus Frequency ............................................ 646
Table 8-5. Master Memory Access Availability ..................................................................... 650
Table 8-6. Flash Register Map ............................................................................................ 651
Table 9-1. μDMA Channel Assignments .............................................................................. 709
Table 9-2. Request Type Support ....................................................................................... 711
Table 9-3. Control Structure Memory Map ........................................................................... 713
Table 9-4. Channel Control Structure .................................................................................. 713
Table 9-5. μDMA Read Example: 8-Bit Peripheral ................................................................ 722
Table 9-6. μDMA Interrupt Assignments .............................................................................. 723
Table 9-7. Channel Control Structure Offsets for Channel 30 ................................................ 724
Table 9-8. Channel Control Word Configuration for Memory Transfer Example ...................... 725
Table 9-9. Channel Control Structure Offsets for Channel 7 .................................................. 726
Table 9-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 726
Table 9-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 728
Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive
Example ............................................................................................................ 728
Table 9-13. μDMA Register Map .......................................................................................... 730
Table 10-1. GPIO Pins With Non-Zero Reset Values .............................................................. 772
Table 10-2. GPIO Pins and Alternate Functions (212BGA) ..................................................... 772
Table 10-3. GPIO Drive Strength Options .............................................................................. 784
Table 10-4. GPIO Pad Configuration Examples ..................................................................... 785
Table 10-5. GPIO Interrupt Configuration Example ................................................................ 786
21December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller