Datasheet

Table 31-3. Signals by Signal Name (continued)
DescriptionBuffer TypePin TypePin Mux / Pin
Assignment
Pin NumberPin Name
GPIO port Q bit 2.TTLI/O-H4PQ2
GPIO port Q bit 3.TTLI/O-M4PQ3
GPIO port Q bit 4.TTLI/O-A13PQ4
GPIO port Q bit 5.TTLI/O-W12PQ5
GPIO port Q bit 6.TTLI/O-U15PQ6
GPIO port Q bit 7.TTLI/O-M3PQ7
GPIO port R bit 0.TTLI/O-N5PR0
GPIO port R bit 1.TTLI/O-N4PR1
GPIO port R bit 2.TTLI/O-N2PR2
GPIO port R bit 3.TTLI/O-V8PR3
GPIO port R bit 4.TTLI/O-P3PR4
GPIO port R bit 5.TTLI/O-P2PR5
GPIO port R bit 6.TTLI/O-W9PR6
GPIO port R bit 7.TTLI/O-R10PR7
GPIO port S bit 0.TTLI/O-D12PS0
GPIO port S bit 1.TTLI/O-D13PS1
GPIO port S bit 2.TTLI/O-B14PS2
GPIO port S bit 3.TTLI/O-A14PS3
GPIO port S bit 4.TTLI/O-V9PS4
GPIO port S bit 5.TTLI/O-T13PS5
GPIO port S bit 6.TTLI/O-U10PS6
GPIO port S bit 7.TTLI/O-R13PS7
GPIO port T bit 0.TTLI/O-W10PT0
GPIO port T bit 1.TTLI/O-V10PT1
GPIO port T bit 2.TTLI/O-E18PT2
GPIO port T bit 3.TTLI/O-F17PT3
4.87-kΩ resistor (1% precision) for Ethernet PHY.AnalogOfixedW15RBIAS
System reset input.TTLIfixedP18RST
Buffered version of the Hibernation module's
32.768-kHz clock. This signal is not output when
the part is in Hibernate mode and before being
configured after power-on reset.
TTLOPC5 (7)
PK7 (5)
PP3 (7)
M1
W16
C12
RTCCLK
SSI module 0 clockTTLI/OPA2 (15)T6SSI0Clk
SSI module 0 frame signalTTLI/OPA3 (15)U5SSI0Fss
SSI Module 0 Bi-directional Data Pin 0 (SSI0TX in
Legacy SSI Mode).
TTLI/OPA4 (15)V4SSI0XDAT0
SSI Module 0 Bi-directional Data Pin 1 (SSI0RX in
Legacy SSI Mode).
TTLI/OPA5 (15)W4SSI0XDAT1
SSI Module 0 Bi-directional Data Pin 2.TTLI/OPA6 (13)V5SSI0XDAT2
SSI Module 0 Bi-directional Data Pin 3.TTLI/OPA7 (13)R7SSI0XDAT3
SSI module 1 clock.TTLI/OPB5 (15)B6SSI1Clk
SSI module 1 frame signal.TTLI/OPB4 (15)C6SSI1Fss
December 13, 20132064
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Signal Tables