Datasheet

Table 31-2. Signals by Pin Number (continued)
DescriptionBuffer TypePin TypePin NamePin Number
GPIO port A bit 3.TTLI/OPA3
U5
I
2
C module 8 data.ODI/OI2C8SDA
SSI module 0 frame signalTTLI/OSSI0Fss
16/32-Bit Timer 1 Capture/Compare/PWM 1.TTLI/OT1CCP1
UART module 4 transmit.TTLOU4Tx
GPIO port F bit 0.TTLI/OPF0
U6
Ethernet 0 LED 0.TTLOEN0LED0
Motion Control Module 0 PWM 0. This signal is controlled by
Module 0 PWM Generator 0.
TTLOM0PWM0
SSI Module 3 Bi-directional Data Pin 1 (SSI3RX in Legacy SSI
Mode).
TTLI/OSSI3XDAT1
Trace data 2.TTLOTRD2
GPIO port F bit 7.TTLI/OPF7
U8
LCD Data Pin 2 input/output.TTLI/OLCDDATA02
GPIO port S bit 6.TTLI/OPS6
U10
Ethernet 0 Receive Error.TTLIEN0RXER
QEI module 0 index.TTLIIDX0
LCD Data Pin 8 input/output.TTLI/OLCDDATA08
16/32-Bit Timer 5 Capture/Compare/PWM 0.TTLI/OT5CCP0
GPIO port N bit 7.TTLI/OPN7
U12
LCD Data Pin 12 input/output.TTLI/OLCDDATA12
UART module 1 Request to Send modem flow control output line.TTLOU1RTS
UART module 4 Clear To Send modem flow control input signal.TTLIU4CTS
GPIO port G bit 7.TTLI/OPG7
U14
Ethernet 0 Receive Data Valid.TTLIEN0RXDV
I
2
C module 4 data.ODI/OI2C4SDA
1-Wire Single Bus Pin. This signal is input only if 1-Wire Alternate
Output is enabled.
TTLI/OOWIRE
SSI module 2 clock.TTLI/OSSI2Clk
GPIO port Q bit 6.TTLI/OPQ6
U15
Ethernet 0 Receive Data 1.TTLIEN0RXD1
UART module 1 Data Terminal Ready modem status input signal.TTLOU1DTR
An external input that brings the processor out of Hibernate mode
when asserted.
TTLIWAKE
U18
GPIO port K bit 4.TTLI/OPK4
U19
Ethernet 0 Interrupt from the Ethernet PHY.TTLIEN0INTRN
Ethernet 0 LED 0.TTLOEN0LED0
Ethernet 0 Receive Data 3.TTLIEN0RXD3
EPI module 0 signal 32.TTLI/OEPI0S32
I
2
C module 3 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
ODI/OI2C3SCL
Motion Control Module 0 PWM 6. This signal is controlled by
Module 0 PWM Generator 3.
TTLOM0PWM6
December 13, 20132050
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Signal Tables