Datasheet

Table 31-2. Signals by Pin Number (continued)
DescriptionBuffer TypePin TypePin NamePin Number
GPIO port Q bit 7.TTLI/OPQ7
M3
UART module 1 Ring Indicator modem status input signal.TTLIU1RI
GPIO port Q bit 3.TTLI/OPQ3
M4
EPI module 0 signal 23.TTLI/OEPI0S23
SSI Module 3 Bi-directional Data Pin 1 (SSI3RX in Legacy SSI
Mode).
TTLI/OSSI3XDAT1
16/32-Bit Timer 7 Capture/Compare/PWM 1.TTLI/OT7CCP1
Ground reference for logic and I/O pins.Power-GND
M8
Ground reference for logic and I/O pins.Power-GND
M9
Ground reference for logic and I/O pins.Power-GND
M10
Positive supply for I/O and some logic.Power-VDD
M11
Positive supply for I/O and some logic.Power-VDD
M12
GPIO port G bit 3.TTLI/OPG3
M16
Ethernet 0 Transmit Enable.TTLOEN0TXEN
I
2
C module 2 data.ODI/OI2C2SDA
SSI Module 2 Bi-directional Data Pin 2.TTLI/OSSI2XDAT2
An output that indicates the processor is in Hibernate mode.TTLOHIB
M17
GPIO port M bit 4.TTLI/OPM4
M18
Ethernet 0 Reference Clock.TTLI/OEN0RREF_CLK
16/32-Bit Timer 4 Capture/Compare/PWM 0.TTLI/OT4CCP0
Tamper signal 3.TTLI/OTMPR3
UART module 0 Clear To Send modem flow control input signal.TTLIU0CTS
GPIO port J bit 6.TTLI/OPJ6
N1
LCD AC bias or latch enable in Raster mode; Primary chip select
(CS0)/Primary Enable (E0) in LIDD MPU/Hitachi mode
TTLOLCDAC
UART module 4 Request to Send modem flow control output line.TTLOU4RTS
GPIO port R bit 2.TTLI/OPR2
N2
I
2
C module 2 clock. Note that this signal has an active pull-up. The
corresponding port pin should not be configured as open drain.
ODI/OI2C2SCL
LCD Line Clock or HSYNC in Raster mode; Write Strobe or
Direction bit in LIDD mode
TTLOLCDLP
Motion Control Module 0 PWM 2. This signal is controlled by
Module 0 PWM Generator 1.
TTLOM0PWM2
GPIO port R bit 1.TTLI/OPR1
N4
I
2
C module 1 data.ODI/OI2C1SDA
LCD Frame Clock or VSYNC in Raster mode; Address Latch
Enable in LIDD mode
TTLOLCDFP
Motion Control Module 0 PWM 1. This signal is controlled by
Module 0 PWM Generator 0.
TTLOM0PWM1
UART module 4 receive.TTLIU4Rx
December 13, 20132046
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Signal Tables