Datasheet

List of Tables
Table 1. Revision History .................................................................................................. 53
Table 2. Documentation Conventions ................................................................................ 55
Table 1-1. TM4C129XNCZAD Microcontroller Features ......................................................... 58
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 94
Table 2-2. Processor Register Map ....................................................................................... 95
Table 2-3. PSR Register Combinations ............................................................................... 101
Table 2-4. Memory Map ..................................................................................................... 112
Table 2-5. Memory Access Behavior ................................................................................... 117
Table 2-6. SRAM Memory Bit-Banding Regions ................................................................... 119
Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................. 119
Table 2-8. Exception Types ................................................................................................ 124
Table 2-9. Interrupts .......................................................................................................... 125
Table 2-10. Exception Return Behavior ................................................................................. 133
Table 2-11. Faults ............................................................................................................... 134
Table 2-12. Fault Status and Fault Address Registers ............................................................ 135
Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 137
Table 3-1. Core Peripheral Register Regions ....................................................................... 144
Table 3-2. Memory Attributes Summary .............................................................................. 148
Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 150
Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 151
Table 3-5. AP Bit Field Encoding ........................................................................................ 151
Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 152
Table 3-7. QNaN and SNaN Handling ................................................................................. 155
Table 3-8. Peripherals Register Map ................................................................................... 156
Table 3-9. Interrupt Priority Levels ...................................................................................... 181
Table 3-10. Example SIZE Field Values ................................................................................ 209
Table 4-1. JTAG_SWD_SWO Signals (212BGA) ................................................................. 218
Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 220
Table 4-3. JTAG Instruction Register Commands ................................................................. 226
Table 5-1. System Control & Clocks Signals (212BGA) ........................................................ 230
Table 5-2. Reset Sources ................................................................................................... 231
Table 5-3. Clock Source Options ........................................................................................ 241
Table 5-4. Clock Source State Following POR ..................................................................... 242
Table 5-5. System Clock Frequency ................................................................................... 246
Table 5-6. System Divisor Factors for f
vco
=480 MHz ............................................................ 248
Table 5-7. Actual PLL Frequency ........................................................................................ 249
Table 5-8. Peripheral Memory Power Control ...................................................................... 254
Table 5-9. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 254
Table 5-10. MOSC Configurations ........................................................................................ 257
Table 5-11. System Control Register Map ............................................................................. 258
Table 5-12. MEMTIM0 Register Configuration versus Frequency ............................................ 288
Table 5-13. MOSC Configurations ........................................................................................ 292
Table 5-14. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 311
Table 5-15. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 314
Table 5-16. Module Power Control ........................................................................................ 473
Table 5-17. Module Power Control ........................................................................................ 475
December 13, 201320
Texas Instruments-Advance Information
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