Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsDev KitsPCB design board

1971

These registers control the interrupt and ADC trigger generation capabilities of the PWM generators

(PWM0INTEN controls the PWM generator 0 block, and so on). The events that can cause an

interrupt,or an ADC trigger are:

■ The counter being equal to the load register

■ The counter being equal to zero

■ The counter being equal to the PWMnCMPA register while counting up

■ The counter being equal to the PWMnCMPA register while counting down

■ The counter being equal to the PWMnCMPB register while counting up

■ The counter being equal to the PWMnCMPB register while counting down

Any combination of these events can generate either an interrupt or an ADC trigger, though no

determination can be made as to the actual event that caused an ADC trigger if more than one is

specified. The PWMnRIS register provides information about which events have caused raw

interrupts.

PWMn Interrupt and Trigger Enable (PWMnINTEN)

PWM0 base: 0x4002.8000

Offset 0x044

Type RW, reset 0x0000.0000

16171819202122232425262728293031

reserved

ROROROROROROROROROROROROROROROROType

0000000000000000Reset

0123456789101112131415

INTCNTZEROINTCNTLOAD

INTCMPAUINTCMPADINTCMPBUINTCMPBD

reserved

TRCNTZEROTRCNTLOAD

TRCMPAUTRCMPADTRCMPBUTRCMPBDreserved

RWRWRWRWRWRWRORORWRWRWRWRWRWROROType

0000000000000000Reset

DescriptionResetTypeNameBit/Field

Software should not rely on the value of a reserved bit. To provide

compatibility with future products, the value of a reserved bit should be

preserved across a read-modify-write operation.

0ROreserved31:14

Trigger for Counter=PWMnCMPB Down

DescriptionValue

No ADC trigger is output.0

An ADC trigger pulse is output when the counter matches the

value in the PWMnCMPB register value while counting down.

0RWTRCMPBD13

1975December 13, 2013

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TM4C129XNCZAD Microcontroller