Datasheet

Register 1: PWM Master Control (PWMCTL), offset 0x000
This register provides master control over the PWM generation blocks.
PWM Master Control (PWMCTL)
PWM0 base: 0x4002.8000
Offset 0x000
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
GLOBALSYNC0 GLOBALSYNC1 GLOBALSYNC2 GLOBALSYNC3
reserved
RWRWRWRWROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:4
Update PWM Generator 3
DescriptionValue
No effect.0
Any queued update to a load or comparator register in PWM
generator 3 is applied the next time the corresponding counter
becomes zero.
1
This bit automatically clears when the updates have completed; it cannot
be cleared by software.
0RWGLOBALSYNC33
Update PWM Generator 2
DescriptionValue
No effect.0
Any queued update to a load or comparator register in PWM
generator 2 is applied the next time the corresponding counter
becomes zero.
1
This bit automatically clears when the updates have completed; it cannot
be cleared by software.
0RWGLOBALSYNC22
1945December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller