Datasheet

Register 27: LCD Clock Resets (LCDCLKRESET), offset 0x070
This register contains the Software Resets for each major domain within the LCD.
LCD Clock Resets (LCDCLKRESET)
Base 0x4405.0000
Offset 0x070
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CORELIDDDMAMAINreserved
RWRWRWRWROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
Software Reset for the entire LCD module. This reset affects the L3 clk
and lcd_clk domain.
DescriptionValue
Reset Disabled0
Reset Enabled1
0RWMAIN3
Software Reset for the DMA submodule. This reset affects the L3 clk
domain.
DescriptionValue
Reset Disabled0
Reset Enabled1
0RWDMA2
Software Reset for the LIDD submodule (character displays). This reset
affects the LIDD logic in the lcd_clk domain.
DescriptionValue
Reset Disabled0
Reset Enabled1
0RWLIDD1
Software Reset for the Core, which encompasses the Raster Active
Matrix and Passive Matrix logic. This reset affects the Core (active matrix
and passive matrix raster mode) logic in the lcd_clk domain.
DescriptionValue
Reset Disabled0
Reset Enabled1
0RWCORE0
December 13, 20131914
Texas Instruments-Advance Information
LCD Controller