Datasheet

Register 26: LCD Clock Enable (LCDCLKEN), offset 0x06C
This register contains the Clock enables for each major domain within the LCD.
LCD Clock Enable (LCDCLKEN)
Base 0x4405.0000
Offset 0x06C
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CORELIDDDMAreserved
RWRWRWROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:3
DMA Clock Enable
Software Clock Enable for the LCD DMA
DescriptionValue
Clock Disabled0
Clock Enabled1
0RWDMA2
LIDD Submodule Clock Enable
Software Clock Enable for the LIDD submodule (character displays).
The LIDD submodule runs on the System Clock domain
DescriptionValue
Clock Disabled0
Clock Enabled1
0RWLIDD1
LCD Core Clock Enable
Software Clock Enable for the LCD core, which encompasses the Raster
Active Matrix and Passive Matrix logic.
The Core runs on the System Clock domain.
DescriptionValue
Clock Disabled0
Clock Enabled1
0RWCORE0
1913December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller