Datasheet

Register 25: LCD Interrupt Enable Clear (LCDIENC), offset 0x064
This register provides for the clearing of interrupt enables (Mask bits).
LCD Interrupt Enable Clear (LCDIENC)
Base 0x4405.0000
Offset 0x064
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DONE
RRASTRDONE
SYNCSACBSreservedFIFOUPALLOADreservedEOF0EOF1reserved
RWRWRWRWRORWRWRORWRWROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:10
DMA End-of-Frame 1 Interrupt Enable Clear
Writing 1 will clear interrupt enable. Writing 0 has no effect. Read
indicates enabled status.
DescriptionValue
Disabled0
Enabled1
0RWEOF19
DMA End-of-Frame 0 Interrupt Enable Clear
Writing 1 will clear interrupt enable. Writing 0 has no effect. Read
indicates enabled status.
DescriptionValue
Disabled0
Enabled1
0RWEOF08
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7
DMA Palette Loaded Interrupt Enable Clear
Writing 1 will clear interrupt enable. Writing 0 has no effect. Read
indicates enabled status.
DescriptionValue
Disabled0
Enabled1
0RWPALLOAD6
December 13, 20131910
Texas Instruments-Advance Information
LCD Controller