Datasheet

DescriptionResetTypeNameBit/Field
DMA FIFO Underflow Interrupt Enable Set
Indicates if LCD dithering logic is not supplying data to the FIFO at a
sufficient rate. FIFO has completely emptied and data pin driver logic
has attempted to take added data from FIFO.
Writing 1 will set interrupt enable. Writing 0 has no effect. Read indicates
enabled (masked) status.
DescriptionValue
Disabled0
Enabled1
0RWFIFOU5
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved4
AC Bias Count Interrupt Enable Set
For Passive Matrix Panels Only
AC bias transition counter has decremented to zero, indicating that the
LCDAC line has transitioned the number of times which is specified by
the ACBI control bit-field in the LCDRASTRTIMn register. The counter
is reloaded with the value in ACBI but it is disabled until the user clears
ABCS.
Writing 1 will set interrupt enable. Writing 0 has no effect. Read indicates
enabled (masked) status.
DescriptionValue
Disabled0
Enabled1
0RWACBS3
Frame Synchronization Lost Interrupt Enable Set
Writing 1 will set interrupt enable. Writing 0 has no effect. Read indicates
enabled (masked) status.
DescriptionValue
Disabled0
Enabled1
0RWSYNCS2
Raster Mode Frame Done Interrupt Enable Set
Writing 1 will set interrupt enable. Writing 0 has no effect. Read indicates
enabled (masked) status.
DescriptionValue
Disabled0
Enabled1
0RWRRASTRDONE1
December 13, 20131908
Texas Instruments-Advance Information
LCD Controller