Datasheet

Register 24: LCD Interrupt Mask (LCDIM), offset 0x060
This register provides for the setting of interrupt enables (Mask bits).
LCD Interrupt Mask (LCDIM)
Base 0x4405.0000
Offset 0x060
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DONE
RRASTRDONE
SYNCSACBSreservedFIFOUPALLOADreservedEOF0EOF1reserved
RWRWRWRWRORWRWRORWRWROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:10
DMA End-of-Frame 1 Interrupt Enable Set
Writing 1 will set interrupt enable. Writing 0 has no effect. Read indicates
enabled (mask) status.
DescriptionValue
Disabled0
Enabled1
0RWEOF19
DMA End-of-Frame 0 Interrupt Enable Set
Writing 1 will set interrupt enable. Writing 0 has no effect. Read indicates
enabled (masked) status.
DescriptionValue
Disabled0
Enabled1
0RWEOF08
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7
DMA Palette Loaded Interrupt Enable Set
Writing 1 will set interrupt enable. Writing 0 has no effect. Read indicates
enabled (masked) status.
DescriptionValue
Disabled0
Enabled1
0RWPALLOAD6
1907December 13, 2013
Texas Instruments-Advance Information
Tiva
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TM4C129XNCZAD Microcontroller