Datasheet

Register 23: LCD Interrupt Status and Clear (LCDMISCLR), offset 0x05C
This register contains the Interrupt Enable Status. This register returns Masked (Enabled) status
interrupts on a Read. Writing a 1 to a bit will clear the associated interrupt.
LCD Interrupt Status and Clear (LCDMISCLR)
Base 0x4405.0000
Offset 0x05C
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DONE
RRASTRDONE
SYNCSACBSreservedFIFOUPALLOADreservedEOF0EOF1reserved
RWRWRWRWRORWRWRORWRWROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:10
DMA End-of-Frame 1 Enabled Interrupt and Clear
Writing 1 will clear interrupt enable. Writing 0 has no effect Read
indicates enabled (masked) status.
DescriptionValue
Inactive0
Active1
0RWEOF19
DMA End-of-Frame 0 Raw Interrupt and Clear
Writing 1 will clear interrupt enable. Writing 0 has no effect. Read
indicates enabled (masked) status.
DescriptionValue
Inactive0
Active1
0RWEOF08
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7
DMA Palette Loaded Enabled Interrupt and Clear
Writing 1 will set status. Writing 0 has no effect. Read indicates enabled
(masked) status.
DescriptionValue
Inactive0
Active1
0RWPALLOAD6
December 13, 20131904
Texas Instruments-Advance Information
LCD Controller