Datasheet

DescriptionResetTypeNameBit/Field
DMA FIFO Underflow Raw Interrupt Status and Set
Indicates if LCD dithering logic is not supplying data to the FIFO at a
sufficient rate. FIFO has completely emptied and data pin driver logic
has attempted to take added data from FIFO.
Writing 1 will set status. Writing 0 has no effect. Read indicates raw
status
DescriptionValue
Inactive0
Active1
0RWFIFOU5
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved4
AC Bias Count Raw Interrupt Status and Set
For Passive Matrix Panels Only
AC bias transition counter has decremented to zero, indicating that the
lcd_ac_o line has transitioned the number of times which is specified
by the ACBI control bit-field in the LCDRASTRTIMn register. The counter
is reloaded with the value in ACBI but it is disabled until the user clears
ABCS.
Writing 1 will set status. Writing 0 has no effect. Read indicates raw
status
DescriptionValue
Inactive0
Active1
0RWACBS3
Frame Synchronization Lost Raw Interrupt Status and Set
Writing 1 will set status. Writing 0 has no effect. Read indicates raw
status.
DescriptionValue
Inactive0
Active1
0RWSYNCS2
Raster Mode Frame Done interrupt.
Writing 1 will set status. Writing 0 has no effect. Read indicates raw
status.
DescriptionValue
Inactive0
Active1
0RWRRASTRDONE1
December 13, 20131902
Texas Instruments-Advance Information
LCD Controller