Datasheet

Register 20: LCD DMA Frame Buffer 1 Ceiling Address (LCDDMACAFB1),
offset 0x050
LCD DMA Frame Buffer 1 Ceiling Address (LCDDMACAFB1)
Base 0x4405.0000
Offset 0x050
Type RW, reset 0x0000.0000
16171819202122232425262728293031
FB1CA
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
reservedFB1CA
RORORWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Frame Buffer 1 Ceiling Address pointer.
For raster modes (MODESEL = 1), this register cannot be the same value
as FB1BA.
0x0000.000RWFB1CA31:2
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved1:0
December 13, 20131898
Texas Instruments-Advance Information
LCD Controller