Datasheet

DescriptionResetTypeNameBit/Field

This bit controls the bytelane ordering of the data on the output of the

DMA module. It works in conjunction with the big-endian bit. See the

big-endian description for configuration guidelines.

0RWBYTESWAP3

Software should not rely on the value of a reserved bit. To provide

compatibility with future products, the value of a reserved bit should be

preserved across a read-modify-write operation.

0ROreserved2

Big Endian Enable

Use this bit when the processor is operating in Big Endian mode and

writes to the frame buffers are less than 32-bits wide. Only in this

scenario do we need to change the byte alignment for data coming into

the FIFO from the frame buffer.

DescriptionValue

Big Endian reordering disabled.0

Big Endian reordering enabled.1

The BIGEND and BYTESWAP bits control the byte lane ordering of the

data on the output of the DMA module.

0RWBIGDEND1

Frame Mode

DescriptionValue

One frame buffer (FB0 only) used0

Two frame buffers used,. DMA ping-pongs between FB0 and

FB1 in this mode

0RWFMODE0

December 13, 20131894

Texas Instruments-Advance Information

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