Datasheet

Register 16: LCD DMA Control (LCDDMACTL), offset 0x040
LCD DMA Control (LCDDMACTL)
Base 0x4405.0000
Offset 0x040
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
FMODEBIGDENDreserved
BYTESWAP
BURSTSZreservedFIFORDYreserved
RWRWRORWRWRWRWRORWRWRWROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000ROreserved31:11
DMA FIFO threshold.
The DMA FIFO becomes ready when the number of words specified by
this register from the frame buffer have been loaded.
DescriptionValue
8 words0x0
16 words0x1
32 words0x2
64 words0x3
128 words0x4
256 words0x5
512 words0x6
reserved0x7
0x0RWFIFORDY10:8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7
Burst Size setting for DMA transfers (all DMA transfers are 32 bits wide):
DescriptionValue
reserved0x0-0x1
burst size of 40x2
burst size of 80x3
burst size of 160x4
reserved0x5-0x7
Note: For Raster Mode, configuring BURSTSZ should be done only
after an LCD peripheral reset using the SRLCD register in
System Control. The BURSTSZ field should not be changed
once the LCD DMA is enabled.
0x0RWBURSTSZ6:4
1893December 13, 2013
Texas Instruments-Advance Information
Tiva
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TM4C129XNCZAD Microcontroller