Datasheet

Note that subpictures are only allowed for Active Matrix mode (LCDTFT=1) in LCDRASTRCTL

LCD Raster Subpanel Display 2 (LCDRASTRSUBP2)

Base 0x4405.0000

Offset 0x03C

Type RW, reset 0x0000.0000

16171819202122232425262728293031

reserved

ROROROROROROROROROROROROROROROROType

0000000000000000Reset

0123456789101112131415

DPDMSBLPPTMSBreserved

RWRWRWRWRWRWRWRWRWROROROROROROROType

0000000000000000Reset

DescriptionResetTypeNameBit/Field

Software should not rely on the value of a reserved bit. To provide

compatibility with future products, the value of a reserved bit should be

preserved across a read-modify-write operation.

0x0000.00ROreserved31:9

Lines Per Panel Threshold Bit 10

This register is Bit 10 of the LPPT field in LCDRASTRSUBP1.

0RWLPPTMSB8

Default Pixel Data MSB [23:16]

DPD defines the default value of the pixel data sent to the panel for the

lines until LPPT is reached or after passing the LPPT.

0x00RWDPDMSB7:0

December 13, 20131892

Texas Instruments-Advance Information

LCD Controller