Datasheet

Register 13: LCD Raster Timing 2 (LCDRASTRTIM2), offset 0x034
LCD Raster Timing 2 (LCDRASTRTIM2)
Base 0x4405.0000
Offset 0x034
Type RW, reset 0x0000.0000
16171819202122232425262728293031
ACBIIVSIHS
INVPXLCLK
INVOEPSYNCRF
PXLCLKCTL
MSBLPPHSWreserved
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWROType
0000000000000000Reset
0123456789101112131415
MSBHFPreservedMSBHBPreservedACBF
RWRWRORORWRWRORORWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31
Bits 9:6 of the horizontal sync width field0x0RWHSW30:27
MSB of Lines Per Panel
Bit 10 of the LPP field in LCDRASTRTIM1.
0RWMSBLPP26
Hsync/Vsync Pixel Clock Control On/Off
Note that this bit MUST be programmed to 0 for Passive Matrix displays.
The edge timing is fixed.
DescriptionValue
LCDLP and LCDFP are driven on opposite edges of pixel clock
than the LCD pixel output.
0
LCDLP and LCDFP are driven according to bit 24, PSYNCRF1
0RWPXLCLKCTL25
Program HSYNC/VSYNC Rise or Fall
DescriptionValue
LCDLP and LCDFP are driven on the falling edge of pixel clock
(PXLCLKCTL must be set to 1).
0
LCDLP and LCDFP are driven on the rising edge of pixel clock
(PXLCLKCTL must be set to 1).
1
0RWPSYNCRF24
Invert Output Enable
DescriptionValue
LCDAC pin is active high in active display mode0
LCDAC pin is active low in active display mode1
Active display mode: data driven out of the LCD's data lines on
programmed pixel clock edge where AC-bias is active. Note that INVOE
is ignored in passive display mode.
0RWINVOE23
December 13, 20131888
Texas Instruments-Advance Information
LCD Controller