Datasheet

Register 11: LCD Raster Timing 0 (LCDRASTRTIM0), offset 0x02C
LCD Raster Timing 0 (LCDRASTRTIM0)
Base 0x4405.0000
Offset 0x02C
Type RW, reset 0x0000.0000
16171819202122232425262728293031
HFPHBP
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
reservedMSBPPLPPLHSW
RORORORWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Horizontal Back Porch Lowbits
Bits 7:0 of the horizontal back porch field.
Encoded value (from 1-1024) used to specify the number of pixel clock
periods to add to the beginning of a line transmission before the first set
of pixels is output to the display (programmed value plus 1). Note that
pixel clock is held in its inactive state during the beginning of the line
wait period in passive display mode, and is permitted to transition in
active display mode.
0x00RWHBP31:24
Horizontal Front Porch Lowbits
Encoded value (from 1-1024) used to specify the number of pixel clock
periods to add to the end of a line transmission before line clock is
asserted (programmed value plus 1). Note that pixel clock is held in its
inactive state during the end of line wait period in passive display mode,
and is permitted to transition in active display mode.
0x00RWHFP23:16
Horizontal Sync Pulse Width Lowbits
Bits 5:0 of the horizontal sync pulse width field.
Encoded value (from 1-1024) used to specify the number of pixel clock
periods to pulse the line clock at the end of each line (programmed value
plus 1). Note that pixel clock is held in its inactive state during the
generation of line clock in passive display mode, and is permitted to
transition in active display mode.
0x00RWHSW15:10
Pixels-per-line LSB[9:4]
The PPL field is set to the (number of horizontal pixels -1) divided by
16.
0x00RWPPL9:4
Pixels-per-line MSB[10]
Needed in order to support up to 2048 ppl.
0RWMSBPPL3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved2:0
December 13, 20131886
Texas Instruments-Advance Information
LCD Controller