Datasheet

Register 10: LCD Raster Control (LCDRASTRCTL), offset 0x028
The LCD Raster Control (LCDRASTRCTL) register is used to configure the features of Raster
Mode.
LCD Raster Control (LCDRASTRCTL)
Base 0x4405.0000
Offset 0x028
Type RW, reset 0x0000.0000
16171819202122232425262728293031
REQDLYPALMODENIBMODETFTMAP
FRMBUFSZ
TFT24
TFT24UPCK
reserved
RWRWRWRWRWRWRWRWRWRWRWROROROROROType
0000000000000000Reset
0123456789101112131415
LCDENLCDBWreservedLCDTFTRDORDERMONO8BreservedREQDLY
RWRWRORORORORORWRWRWRORORWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:27
24-bit TFT Mode Packing
This bit is only used when TFT24 and LCDTFT are both set to 1.
If TFT24UPCK is clear, 24-bit pixels are packed in 32-bit boundaries
which means four pixels are saved in every three words, as shown
below.
Word0: pix1[7:0],pix0[23:0]
Word1: pix2[15:0],pix1[23:8]
Word2: pix3[23:0],pix2[23:16]
Refer to Figure 26-5 on page 1860 for information on how the pixels are
packed.
If this bit is set to 1, then 24-bit pixels are stored unpacked in DDR with
the uppermost byte unused, as shown below:
Word0: Unused[7:0],pix0[23:0]
Word1: Unused[7:0],pix1[23:0]
Word2: Unused[7:0],pix2[23:0]
Word3: Unused[7:0], pix3[23:0]
DescriptionValue
24-bit pixels are packed into 32 bit boundaries, which means 4
pixels are saved in every three words
0
24-bit pixels are stored unpacked in DDR with the uppermost
byte unused
1
0RWTFT24UPCK26
December 13, 20131882
Texas Instruments-Advance Information
LCD Controller