Datasheet

Register 8: LIDD CS1 Address Read/Write Initiation (LIDDCS1ADDR), offset
0x020
This register contains the read and write address of the current access enabled by CS1 (LCDAC).
LIDD CS1 Address Read/Write Initiation (LIDDCS1ADDR)
Base 0x4405.0000
Offset 0x020
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CS1ADDR
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
LCD Address Bus
The LCD Controller supports a shared Address/Data output bus. A write
to this register would initiate a bus write transaction. A read from this
register would initiate a bus read transaction.
CPU reads and writes to this register are not permitted if the LIDD
module is in DMA mode (DMAEN bit set in the LIDDCTRL register). If
the LIDD is being used as a generic bus interface, writing to this register
can store CS1ADDR to an external transparent latch holding a 16-bit
address.
If the LIDD is being used to interface with a character based LCD panel
in Hitachi configuration mode, reading and writing to this register can
be used to access the command instruction area of the panel.
0x0000RWCS1ADDR15:0
December 13, 20131880
Texas Instruments-Advance Information
LCD Controller