Datasheet

Register 7: LIDD CS1 Configuration (LIDDCS1CFG), offset 0x01C
The LIDD CS1 Configuration (LIDDCS1CFG) register defines the timings for the read and write
strobes with respect to CS1.
LIDD CS1 Configuration (LIDDCS1CFG)
Base 0x4405.0000
Offset 0x01C
Type RW, reset 0x0044.0044
16171819202122232425262728293031
RDSUWRHOLDWRDURWRSU
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0010001000000000Reset
0123456789101112131415
GAPRDHOLDRDDURRDSU
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0010001000000000Reset
DescriptionResetTypeNameBit/Field
Write Strobe (WR) Set-Up Cycles
When performing a write access, this field defines the number of
LCDMCLK cycles that Data Bus/Pad Output Enable, ALE, DIR, and CS1
have to be ready before WR (LCDLP) is asserted. The minimum value
is 0x0.
0x0RWWRSU31:27
Write Strobe (WR) Duration Cycles
Field value defines the number of LCDMCLK cycles for which WR (LCDLP)
is held active when performing a write access. The minimum value is
0x1.
0x2RWWRDUR26:21
Write Strobe (WR) Hold cycles.
Field value defines the number of LCDMCLK cycles for which Data
Bus/Pad Output Enable, ALE, the DIR, and CS1 signals are held after
WR (LCDLP) is deasserted when performing a write access. The
minimum value is 0x1.
0x2RWWRHOLD20:17
Read Strobe (RD) Set-Up cycles.
When performing a read access, this field defines the number of
LCDMCLK cycles that Data Bus/Pad Output Enable, ALE, the DIR, and
CS1 signals have to be ready before RD (LCDCP) is asserted.
0x0RWRDSU16:12
Read Strobe (RD) Duration cycles.
Field value defines the number of LCDMCLK cycles for which RD
(LCDCP) is held active when performing a read access. The minimum
value is 0x1.
0x1RWRDDUR11:6
Read Strobe (RD) Hold cycles.
Field value defines the number of LCDMCLK cycles for which Data
Bus/Pad Output Enable, ALE, DIR, and CS1 signals are held after RD
(LCDCP) is deasserted when performing a read access. The minimum
value is 0x1.
0x1RWRDHOLD5:2
Field value defines the number of LCDMCLK cycles (GAP + 1) between
the end of one CS1 (LCDAC) device access and the start of another CS0
(LCDAC) device access unless the two accesses are both reads. In this
case, this delay is not incurred. The minimum value is 0x0.
0x0RWGAP1:0
1879December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller