Datasheet

This register contains the read and write data of the current access enabled by CS0 (LCDAC).

LIDD CS0 Data Read/Write Initiation (LIDDCS0DATA)

Base 0x4405.0000

Offset 0x018

Type RW, reset 0x0000.0000

16171819202122232425262728293031

reserved

ROROROROROROROROROROROROROROROROType

0000000000000000Reset

0123456789101112131415

CS0DATA

RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType

0000000000000000Reset

DescriptionResetTypeNameBit/Field

Software should not rely on the value of a reserved bit. To provide

compatibility with future products, the value of a reserved bit should be

preserved across a read-modify-write operation.

0x0000ROreserved31:16

LCD Data Read/Write

The LCD Controller supports a shared Address/Data output bus. A write

to this register initiates a bus write transaction. A read from this register

initiates a bus read transaction.

CPU reads and writes to this register are not permitted if the LIDD

module is in DMA mode (DMAEN bit set in the LIDDCTRL register).

If the LIDD is being used as a generic bus interface, writing to this

16-bit address.

If the LIDD is being used to interface with a character based LCD panel

in Hitachi configuration mode, reading and writing to this register can

be used to access the data area of the panel.

0x0000RWCS0DATA15:0

December 13, 20131878

Texas Instruments-Advance Information

LCD Controller