Datasheet

Register 4: LCD LIDD CS0 Configuration (LIDDCS0CFG), offset 0x010
The LIDD CS0 Configuration (LIDDCS0CFG) register defines the timings for the read and write
strobes with respect to CS0.
LCD LIDD CS0 Configuration (LIDDCS0CFG)
Base 0x4405.0000
Offset 0x010
Type RW, reset 0x0044.0044
16171819202122232425262728293031
RDSUWRHOLDWRDURWRSU
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0010001000000000Reset
0123456789101112131415
GAPRDHOLDRDDURRDSU
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0010001000000000Reset
DescriptionResetTypeNameBit/Field
Write Strobe (WR) Set-Up Cycles
When performing a write access, this field defines the number of MCLK
cycles that the LCDDATA bus, output enable, ADE, DIR and CS0 signals
have to be ready before the write strobe. The minimum value is 0x0.
0x0RWWRSU31:27
Write Strobe (WR) Duration Cycles
This field value defines the number of MCLK cycles for which the write
strobe is held active when performing a write access. The minimum
value is 0x1.
0x2RWWRDUR26:21
Write Strobe (WR) Hold cycles.
This field value defines the number of MCLK cycles for which the
LCDDATA bus, output enable, ALE, DIR and CS0 signals are held after
the write strobe is deasserted when performing a write access. The
minimum value is 0x1.
0x2RWWRHOLD20:17
Read Strobe (RD) Set-Up cycles.
When performing a read access, this field defines the number of MCLK
cycles that the LCDDATA bus, output enable, ALE, DIR and CS0 signals
have to be ready before the read strobe is asserted.
0x0RWRDSU16:12
Read Strobe (RD) Duration cycles.
This field defines the number of MCLK cycles for which the read strobe
is held active when performing a read access. The minimum value is
0x1.
0x1RWRDDUR11:6
Read Strobe (RD) Hold cycles.
This field defines of MCLK cycles for which the LCDDATA bus, output
enable, ALE, DIR and CS0 signals are held after the read strobe is
deasserted when performing a read access. The minimum value is 0x1.
0x1RWRDHOLD5:2
Field value defines the number of LCDMCLK cycles (GAP +1) between
the end of one CS0 (LCDAC) device access and the start of another CS0
(LCDAC) device access unless the two accesses are both reads. In this
case, this delay is not incurred. The minimum value is 0x0.
0x0RWGAP1:0
December 13, 20131876
Texas Instruments-Advance Information
LCD Controller