Datasheet

Register 2: LCD Control (LCDCTL), offset 0x004
The LCD Control (LCDCTL) register configures the mode, clock frequencies and restart behavior
of the LCD Controller.
LCD Control (LCDCTL)
Base 0x4405.0000
Offset 0x004
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
LCDMODE
UFLOWRST
reservedCLKDIV
RWRWRORORORORORORWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
Clock Divisor
This field contains a value (from 0-255) used to specify the frequency
of the pixel clock, LCDCP (in Raster Mode) or MCLK ( in LIDD mode).
The equation for the two clock outputs is: SYSCLK/CLKDIV, where:
■ LCDCP can range from SYSCLK/2 to SYSCLK/255. CLKDIV = 0x0
or CLKDIV = 0x1 are not allowed.
■ MCLK can vary from SYSCLK to SYSCLK/255 (using CLKDIV =
0x0 or CLKDIV = 0x1 sets MCLK = SYSCLK.
See Table 26-10 on page 1872 for f
SYSCLK
to f
LCDCP
frequency conversions
based on CLKDIV value.
0x00RWCLKDIV15:8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved7:2
Underflow Restart
DescriptionValue
On an underflow, software must restart the module.0
On an underflow, the hardware restarts the module on the next
frame.
1
0RWUFLOWRST1
LCD Mode Select
DescriptionValue
LCD Controller is operating in LIDD Mode0
LCD Controller is operating in Raster Mode1
0RWLCDMODE0
1871December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller