Datasheet

format. In packed format, four 24 bit pixels are stored in 3 contiguous 32-bit words (also called a
quad-pixel triplet) in DDR, as show in Figure 26-5 on page 1860.
Figure 26-5. 24 bpp Packed Data Format
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Pixel 1 [7:0]
031
0731 8
Pixel 0 [23:0]
Pixel 2 [15:0] Pixel 1 [23:8]
Pixel 2 [23:16]Pixel 3 [23:0]
Word X
Word X + 1
Word X + 2
16 15
When using a 24 bit packed format, four consecutive pixels provide three word-aligned accesses
for the DMA. If the MSBPPL and PPL bits in the LCDRASTRTIM0 register are programmed to a
multiple of 16, then the MSBLPP and LPP bits of the LCDRASTRTIM1and LCDRASTRTIM2 register
must follow a multiple of 16 so that the DMA can access the data using word-aligned accesses.
When LCDTFT = 0x1, TFT24UPCK = 0x1 and TFT24 = 0x1 in the LCDRASTRCTL register, 24 bit
unpacked format is used. In this mode, each 24 bpp data is stored in a 32 bit word, with the upper
8 bits unused. Figure 26-6 on page 1860 shows the unpacked implementation.
Figure 26-6. 24 bpp Unpacked Data Format
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0x00 Pixel 0 [23:0]Word X
Word X + 1
Word X + 2
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0x00 Pixel 1 [23:0]
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0x00 Pixel 2 [23:0]
For 24 bpp color components, data is stored in the DDR in B-G-R order with each color representing
8 bits. When the data is transferred to the LCD pixel data bus (LCDDATA[23:0]), the output is
transposed such that a portion of the color components are now displayed on LCDDATA [15:0] in
RGB565 format. The three least significant bits of the RGB 24-bit data are prepended to RGB565
data on LCDDATA[23:15]. The transposition of data is shown in Figure 26-7 on page 1861.
December 13, 20131860
Texas Instruments-Advance Information
LCD Controller