Datasheet

Table 26-5. Operation Modes Supported by Raster Controller
DescriptionSignal NameRASTERCTRL
[9, 7, 1]
Data
Bus
Width
Interface
Data BusLCDDATA[3:0]
0014
Passive
(STN)
Mono 4-bit
Pixel ClockLCDCP
Horizontal clock (line clock)LCDLP
Vertical clock (frame clock)LCDFP
AC BiasLCDAC
Not usedLCDMCLK
Data BusLCDDATA[7:0]
1018
Passive
(STN)
Mono 8-bit
Pixel ClockLCDCP
Horizontal clock (line clock)LCDLP
Vertical clock (frame clock)LCDFP
AC BiasLCDAC
Not usedLCDMCLK
Data BusLCDDATA[7:0]
1008
Passive
(STN)
Color
Pixel ClockLCDCP
Horizontal clock (line clock)LCDLP
Vertical clock (frame clock)LCDFP
AC BiasLCDAC
Not usedLCDMCLK
Data BusLCDDATA[15:0]
x1016
Active
(TFT)
Color
Pixel ClockLCDCP
Horizontal clock (line clock)LCDLP
Vertical clock (frame clock)LCDFP
AC BiasLCDAC
Not usedLCDMCLK
26.3.3.1 Logical Data Path
The block diagram of the Raster controller is shown in Figure 26-1 on page 1848. Figure
26-2 on page 1855 illustrates its logical data path for various operation modes (passive (STN) versus
active (TFT) and various BPP size). Figure 26-2 on page 1855 shows that:
■ The gray-scaler/serializer and output FIFO blocks are bypassed in active (TFT) modes.
■ The palette is bypassed in both 12- and 16-BPP modes.
December 13, 20131854
Texas Instruments-Advance Information
LCD Controller