Datasheet

■ Frame Synchronization lost: This error happens when the DMA engine attempts to read what it
believes to be the first word of the video buffer but the data cannot be recognized as such. This
situation can be caused by an invalid frame buffer address or an invalid BPP value. The SYNC
bit in the IRQSTATUS_RAW register is set when such an error is detected. This field is cleared
by disabling the Raster Controller (clearing the LCDEN bit in LCD Raster Control
(LCDRASTRCTL) register).
■ Palette loaded: This interrupt can be generated when the palette is loaded into the memory by
the DMA engine. At the same time, the PALLOAD bit in the LCD Interrupt Raw Status and Set
Register (LCDRISSET) register is set. In data-only (PALMODE = 0x2) and palette-plus-data
(PALMODE = 0x0) modes, writing 0 to this bit clears the interrupt. In the palette-only (PALMODE
= 0x1) mode, this bit is cleared by disabling the Raster Controller (clearing the LCDEN bit in the
LCD Raster Control (LCDRASTRCTL) register).
■ AC Bias transition: If the ACBI field in the LCD Raster Timing 2 (LCDRASTRTIM2) register is
programmed with a nonzero value, an internal counter is loaded with this value and starts to
decrement each time LCDAC (AC-bias signal) switches its state. When the counter reaches zero,
the ACBS bit in the LCD Interrupt Raw Status and Set Register (LCDRISSET) register is set,
which delivers an interrupt signal to the system interrupt controller (if the interrupt is enabled.)
The counter reloads the value in ACBI field, but does not start to decrement until the ABC bit is
cleared by writing 0 to this bit.
■ Frame transfer completed: When one frame of data is transferred completely, the DONE bit in
the LCD Interrupt Raw Status and Set Register (LCDRISSET) register is set. This bit is cleared
by disabling the Raster Controller (clearing the LCDEN bit in LCD Raster Control
(LCDRASTRCTL) register). The EOF0 and EOF1 bits in LCD Interrupt Raw Status and Set
Register (LCDRISSET) register are set accordingly.
Note that the function enable bits are in the in LCD Raster Control (LCDRASTRCTL) register and
must be set in order to generate an interrupt to the CPU.
26.3.2 LIDD Bus Operation
The integrated LCD Interface Display Drive (LIDD) Controller has programmable timing parameters
that support a wide variety of character-based LCD panels. Alternatively, the DMA module can be
used to mimic the CPU and perform a sequence of write-only data bus transactions to the
character-based LCD panel.
LIDD mode is enabled by clearing the LCDMODE bit in the LCD Control (LCDCTL) register.
LIDD Controller operation is summarized as follows:
■ During initialization, the LCD LIDD CS0 Configuration (LIDDCS0CFG) and LCD LIDD CS1
Configuration (LIDDCS1CFG) registers are configured to match the requirements of the LCD
panel being used.
■ During normal operation, the CPU writes display data to the LIDD CS0 Data Read/Write Initiation
(LIDDCS0DATA) and LIDD CS1 Data Read/Write Initiation (LIDDCS1DATA) registers. The
LIDD interface converts the CPU write into the proper signal transition sequence for the display,
as programmed earlier. Note that the first CPU write should send the beginning address of the
update to the LCD panel and the subsequent writes update data at display locations starting
from the first address and continuing sequentially. Note that DMA may be used instead of CPU.
December 13, 20131852
Texas Instruments-Advance Information
LCD Controller