Datasheet

When the Raster Controller is used, the LCD DMA engine reads data from a frame buffer and writes
it to the input FIFO. The Raster Controller requests data from the FIFO for frame refresh, so the
DMA is used to keep the FIFO filled.
When the LIDD controller is used, the LCD DMA engine accesses the LIDD controller's address
and/or data registers. The following steps are needed to configure the DMA engine:
1. Configure the data format in the LCD DMA Control (LCDDMACTL) register, offset 0x040.
2. Configure frame buffer 0 by programming the LCD DMA Frame Buffer 0 Base Address
(LCDDMABAFB0) register, offset 0x044, and the LCD DMA Frame Buffer 0 Ceiling Address
(LCDDMACAFB0) register, offset 0x048
3. Configure frame buffer 1 by programming the LCD DMA Frame Buffer 1 Base Address
(LCDDMABAFB1) register, offset 0x04C, and the LCD DMA Frame Buffer 1 Ceiling Address
(LCDDMACAFB1) register, offset 0x050.
In addition, depending on whether the application is operating in LIDD mode or Raster Mode, the
LCDLIDDCTL or the LCDRASTRCTL register should be configured appropriately, along with all of
the timing registers. To enable DMA transfers, the DMAEN bit in the LCDLIDDCTL or the LCDEN bit
in the LCDRASTRCTL register should be written with a 1.
26.3.1.1 Interrupts
Interrupts in this LCD module are related to DMA engine operation. Five registers are used to control
and monitor the interrupts:
■ LCDLIDDCTL and LCDRASTRCTL registers enable and disable individual features that can
generate interrupts.
■ The LCD Interrupt Raw Status and Set Register (LCDRISSET) register, offset 0x058, collects
all of the interrupt status information.
■ The LCD Interrupt Status and Clear (LCDMISCLR) register, offset 0x05C, is used to read and
clear the status of the masked interrupt triggers.
■ The LCD Interrupt Mask (LCDIM) register, offset 0x060, is used to control whether an interrupt
source is masked or not.
LIDD Mode
When operating in LIDD mode, the DMA engine generates one interrupt signal every time the
specified frame buffer has been transferred completely. The EOF1, EOF0 and DONE bits of the
LCDRISSET register reflect the interrupt signal, regardless of whether or not the interrupt is enabled.
Raster Mode
When operating in Raster mode, the DMA engine can generate the interrupts in the following
scenarios:
■ Output FIFO under-run: This interrupt occurs when the DMA engine cannot keep up with the
data rate consumed by the LCD (which is determined by the LCDCP.) This is likely due to a
system memory throughput issue or an incorrect LCDCP setting. The FIFOU bit in LCD Interrupt
Raw Status and Set Register (LCDRISSET) register is set when this error occurs. This bit is
cleared by disabling the Raster Controller (that is, clearing the LCDEN bit in LCD Raster Control
(LCDRASTRCTL) register).
1851December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller