Datasheet

Table 26-2. LCD External Signal Details (continued)
FunctionModeTypeSignal
This signal functions as the pixel clock the LCD uses to clock the pixel data
into the line shift register. In passive mode, the pixel clock transitions only
when valid data is available on the data lines. In active mode, the pixel clock
transitions continuously, and the LCDAC pin is used as an output enable to
signal when data is available on the LCD pin.
Raster Mode
Output
LCDCP
(Pixel
clock)
This signal functions as a read strobe (RS) or read/write strobe (RS/WS)
depending on the interface mode.
LIDD Mode
This signal functions as the AC-bias used to trigger the LCD to switch the
polarity of the power supplies to the row and column axis of the screen to
counteract DC offset. The signal is used in TFT mode as the output enable
to signal when data is latched from the data pins using the pixel clock.
LIDD Character: Primary Enable Strobe (E0)
LIDD Graphics: Chip Select 0 (CS0)
Raster Mode
OutputLCDAC
This signal functions as the primary enable (E0) or HItachi mode and the
primary chip select (CS0) depending on the interface mode.
LIDD Mode
This signal is not used in Raster mode, but is used as a secondary Enable
Strobe (E1) or Chip Select (CS1) depending on the interface mode.
LIDD ModeOUTLCDMCLK
These signals function as the LCD data bus providing 4-, 8-, 16-, or 24-bit
data path. For monochrome displays, each signal represents a pixel; for
passive color displays, groupings of three signals represent one pixel (red,
green, and blue). LCDDATA[3:0] are used for monochrome displays of 2,
4, and 8 BPP; LCDDATA[7:0] are used for color STN displays and
LCDDATA[15:0] or LCDDATA[23:0] are used for active (TFT) mode.
Raster ModeOutput
LCDDATA
These signals function as the read and write path for the command and data
registers.
LIDD ModeOutput/Input
Table 26-3 on page 1850 details MODESEL programming for the alternate pin functions in LIDD mode.
For further programming information refer to the LCDLIDDCTL register.
Table 26-3. LCD Alternate Signal Functions in LIDD Mode
MODE = 0x4MODE = 0x3MODE = 0x2MODE = 0x1MODE = 0x0PIN
N/ARSRSRS/WSRS/WSLCDCP
DIRWSWSDIRDIRLCDLP
ALEALEALEALEALELCDFP
E0CS0CS0CS0CS0LCDAC
E1CS1MCLKCS1MCLKLCDMCLK
26.3 Functional Description
The following sections describe the functional capability of the LCD Controller
26.3.1 LCD DMA Engine
The LCD DMA engine provides the capability to output graphics data to constantly refresh the
external LCD display, without burdening the CPU, via interrupts or a firmware timer. It operates on
one or two frame buffers, which are set up during initialization. Using two frame buffers (ping-pong
buffers) enables the simultaneous operation of outputting the current video frame to the external
display and updating the next video frame. The ping-pong buffering approach is preferred in most
applications.
December 13, 20131850
Texas Instruments-Advance Information
LCD Controller