Datasheet

Figure 26-12. 1/2/4/8 bpp Dither Output ................................................................................. 1862
Figure 26-13. Monchrome and Color Output ........................................................................... 1865
Figure 26-14. Example of Subpicture ..................................................................................... 1866
Figure 26-15. Subpicture Output with HOLS Bit Variations ....................................................... 1866
Figure 27-1. Analog Comparator Module Block Diagram ....................................................... 1916
Figure 27-2. Structure of Comparator Unit ............................................................................ 1917
Figure 27-3. Comparator Internal Reference Structure .......................................................... 1918
Figure 28-1. PWM Module Diagram ..................................................................................... 1933
Figure 28-2. PWM Generator Block Diagram ........................................................................ 1933
Figure 28-3. PWM Count-Down Mode .................................................................................. 1936
Figure 28-4. PWM Count-Up/Down Mode ............................................................................. 1936
Figure 28-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1937
Figure 28-6. PWM Dead-Band Generator ............................................................................. 1937
Figure 29-1. QEI Block Diagram .......................................................................................... 2011
Figure 29-2. QEI Input Signal Logic ...................................................................................... 2012
Figure 29-3. Quadrature Encoder and Velocity Predivider Operation ...................................... 2014
Figure 30-1. 212-Ball BGA Package Pin Diagram (Top View) ................................................. 2033
Figure 32-1. Load Conditions ............................................................................................... 2105
Figure 32-2. JTAG Test Clock Input Timing ........................................................................... 2107
Figure 32-3. JTAG Test Access Port (TAP) Timing ................................................................ 2107
Figure 32-4. Power and Brown-Out Assertions vs V
DDA
Levels .............................................. 2109
Figure 32-5. Power and Brown-Out Assertions vs V
DD
Levels ................................................ 2110
Figure 32-6. POK Assertion vs V
DDC
................................................................................... 2111
Figure 32-7. POR-BOR V
DD
Glitch Response ....................................................................... 2111
Figure 32-8. POR-BOR V
DD
Droop Response ...................................................................... 2112
Figure 32-9. Digital Power-On Reset Timing ......................................................................... 2113
Figure 32-10. Brown-Out Reset Timing .................................................................................. 2113
Figure 32-11. External Reset Timing (RST) ............................................................................ 2113
Figure 32-12. Software Reset Timing ..................................................................................... 2114
Figure 32-13. Watchdog Reset Timing ................................................................................... 2114
Figure 32-14. MOSC Failure Reset Timing ............................................................................. 2114
Figure 32-15. Hibernation Module Timing ............................................................................... 2124
Figure 32-16. ESD Protection ................................................................................................ 2128
Figure 32-17. ESD Protection for Non-Power Pins (Except WAKE Signal) ................................ 2129
Figure 32-18. SDRAM Initialization and Load Mode Register Timing ........................................ 2130
Figure 32-19. SDRAM Read Timing ....................................................................................... 2131
Figure 32-20. SDRAM Write Timing ....................................................................................... 2131
Figure 32-21. Host-Bus 8/16 Asynchronous Mode Read Timing ............................................... 2132
Figure 32-22. Host-Bus 8/16 Asynchronous Mode Write Timing ............................................... 2132
Figure 32-23. Host-Bus 8/16 Mode Asynchronous Muxed Read Timing .................................... 2133
Figure 32-24. Host-Bus 8/16 Mode Asynchronous Muxed Write Timing .................................... 2133
Figure 32-25. General-Purpose Mode Read and Write Timing ................................................. 2134
Figure 32-26. PSRAM Single Burst Read ............................................................................... 2135
Figure 32-27. PSRAM Single Burst Write ............................................................................... 2136
Figure 32-28. ADC External Reference Filtering ..................................................................... 2142
Figure 32-29. ADC Input Equivalency Diagram ....................................................................... 2142
Figure 32-30. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................. 2143
December 13, 201318
Texas Instruments-Advance Information
Table of Contents