Datasheet

Register 72: Ethernet PHY Basic Mode Control - MR0 (EPHYBMCR), address
0x000
This register describes the basic mode controls available to the EPHY. The reset state of the ANEN
bit is controlled by the EMACPC register.
Ethernet PHY Basic Mode Control - MR0 (EPHYBMCR)
Base n/a
Address 0x000
Type RW, reset 0x3100
0123456789101112131415
reservedCOLLTSTDUPLEXM
RESTARTAN
ISOLATEPWRDWNANENSPEED
MIILOOPBK
MIIRESET
RORORORORORORORWRWRWRWRWRWRWRWRWType
0000000010001100Reset
DescriptionResetTypeNameBit/Field
MII Register reset
Writing a 1 to this bit resets the contents of the MII-related registers,
EPHYBMCR (0x000) EPHYANA (0x004) and EPHYANNPTR (0x007)
registers . When the reset operation is done, this bit is cleared to 0
automatically.
DescriptionValue
Normal operation.0
Initiate MII Reset / Reset in Process.1
0RWMIIRESET15
MII Loopback
When MII loopback mode is activated, the transmitter data presented
on MII TXD is looped back to MII RXD internally.
DescriptionValue
Normal operation.0
MII Loopback enabled.1
0RWMIILOOPBK14
Speed Select
When auto-negotiation is disabled writing to this bit allows the port speed
to be selected.
DescriptionValue
10Mbs0
100Mbs1
1RWSPEED13
Auto-Negotiate Enable
DescriptionValue
Auto-Negotiation Disabled – the SPEED bit and the DUPLEXM
bit determine the port speed and duplex mode.
0
Auto-Negotiation Enabled – the SPEED bit and the DUPLEXM bit
of this register are ignored when this bit is set.
1
1RWANEN12
December 13, 20131784
Texas Instruments-Advance Information
Ethernet Controller