Datasheet

DescriptionResetTypeNameBit/Field
When PPSCTRL = 0x3, EN0PPS (4 Hz) is a sequence of:
■ Three clocks of 50 percent duty cycle and 268 ms period
■ Fourth clock of 195 ms period (134 ms low and 61 ms high)
This signaling behavior is because of the non-linear toggling of bits in
the digital rollover mode in the Ethernet MAC System Time -
Nanoseconds (EMACTIMNANO) register.
December 13, 20131744
Texas Instruments-Advance Information
Ethernet Controller