Datasheet

Figure 21-7. High-Speed Data Format .................................................................................. 1435
Figure 21-8. Master Single TRANSMIT ................................................................................ 1439
Figure 21-9. Master Single RECEIVE ................................................................................... 1440
Figure 21-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1441
Figure 21-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1442
Figure 21-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1443
Figure 21-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1444
Figure 21-14. Standard High Speed Mode Master Transmit ..................................................... 1445
Figure 21-15. Slave Command Sequence .............................................................................. 1446
Figure 22-1. 1-Wire Block Diagram ...................................................................................... 1505
Figure 22-2. 1-Wire Reset Protocol ...................................................................................... 1507
Figure 22-3. 1-Wire Master Transmitting a 1 ......................................................................... 1508
Figure 22-4. 1-Wire Master Transmitting a 0' ........................................................................ 1508
Figure 22-5. 1-Wire Master Receiving a 1 Signal from a Slave ............................................... 1509
Figure 22-6. 1-Wire Master Receiving a 0 Signal from a Slave ............................................... 1509
Figure 23-1. CAN Controller Block Diagram .......................................................................... 1535
Figure 23-2. CAN Data/Remote Frame ................................................................................. 1536
Figure 23-3. Message Objects in a FIFO Buffer .................................................................... 1545
Figure 23-4. CAN Bit Time ................................................................................................... 1549
Figure 24-1. Ethernet MAC with Integrated PHY Interface ..................................................... 1586
Figure 24-2. Ethernet MAC and PHY Clock Structure ............................................................ 1589
Figure 24-3. MII Clock Structure .......................................................................................... 1590
Figure 24-4. RMII Clock Structure ........................................................................................ 1591
Figure 24-5. TX DMA Default Operation Using Normal Descriptors ........................................ 1597
Figure 24-6. TX DMA OSF Mode Operation Using Normal Descriptors ................................... 1599
Figure 24-7. RX DMA Operation Flow .................................................................................. 1602
Figure 24-8. Normal Receive and Transmit Descriptor Configuration ...................................... 1605
Figure 24-9. Enhanced Transmit Descriptor Structure ........................................................... 1614
Figure 24-10. Enhanced Receive Descriptor Structure ............................................................ 1619
Figure 24-11. Networked Time Synchronization ...................................................................... 1631
Figure 24-12. System Time Update Using Fine Correction Method .......................................... 1633
Figure 24-13. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path
Correction ....................................................................................................... 1636
Figure 24-14. Wake-Up Frame Filter Register Bank ................................................................ 1644
Figure 24-15. Integrated PHY Diagram .................................................................................. 1649
Figure 24-16. Interface to Ethernet Jack ................................................................................. 1655
Figure 25-1. USB Module Block Diagram ............................................................................. 1839
Figure 26-1. LCD Block Diagram ......................................................................................... 1848
Figure 26-2. LCD Raster Data Path ...................................................................................... 1855
Figure 26-3. Input and Output Clocks ................................................................................... 1856
Figure 26-4. Palette RAM Structure for 1, 2, and 4 Bits Per Pixel ........................................... 1858
Figure 26-5. 24 bpp Packed Data Format ............................................................................. 1860
Figure 26-6. 24 bpp Unpacked Data Format ......................................................................... 1860
Figure 26-7. 24 bpp Color RGB Remapping on LCDDATA[23:0] ............................................. 1861
Figure 26-8. 16 bpp Data Format ......................................................................................... 1861
Figure 26-9. 16 bpp Color Component Ordering .................................................................... 1861
Figure 26-10. 12 bpp Data Format ......................................................................................... 1862
Figure 26-11. 12 bpp Color Component Ordering .................................................................... 1862
17December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller