Datasheet

DescriptionResetTypeNameBit/Field
TX/RX Controller RX FIFO Fill-level Status
This field gives the status of the fill-level of the RX FIFO. The FIFO
threshold is programmed by the TCC field in the Ethernet MAC DMA
Operation Mode (EMACDMAOPMODE) register.:
DescriptionValue
RX FIFO Empty0x0
RX FIFO fill level is below the flow-control deactivate threshold0x1
RX FIFO fill level is above the flow-control activate threshold0x2
RX FIFO Full0x3
0x0RORXF9:8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7
TX/RX Controller Read Controller State
This field gives the state of the RX FIFO read Controller:
DescriptionValue
IDLE state0x0
Reading frame data0x1
Reading frame status (or timestamp)0x2
Flushing the frame data and status0x3
0x0RORRC6:5
TX/RX Controller RX FIFO Write Controller Active Status
DescriptionValue
The MTL RX FIFO Write Controller is inactive.0
MTL RX FIFO Write Controller is active and is transferring a
received frame to the FIFO.
1
0RORWC4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
MAC Receive Frame Controller FIFO Status
When high, this field indicates the active state of the small FIFO Read
and Write controllers of the MAC Receive Frame Controller Module.
0x0RORFCFC2:1
MAC MII Receive Protocol Engine Status
DescriptionValue
MAC MII receive protocol engine is not actively receiving data.0
Indicates that the MAC MII receive protocol engine is actively
receiving data and not in IDLE state.
1
0x0RORPE0
1685December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller