Datasheet

The MAC module and registers are enabled and powered at reset. When reset has completed, the
application should enable the clock to the Ethernet MAC by setting the R0 bit in the Ethernet
Controller Run Mode Clock Gating Control (RCGCEMAC) register at System Control Module
offset 0x69C. To enable the PHY with its default interface configuration as defined by the Ethernet
MAC Peripheral Configuration Register (EMACPC) register, do the following:
1. To hold the PHY from transmitting energy on the line during configuration, set the PHYHOLD bit
to 1 in the EMACPC register.
2. Enable the clock to the PHY module by writing 0x0000.0001 to the Ethernet PHY Run Mode
Clock Gating Control (RCGCEPHY) register at offset 0x630 and then delay for 30 clock cycles
If a custom configuration of the PHY is required, the application can program the configuration
registers after reset. The steps for custom configuration are as follows:
1. To hold the PHY from transmitting energy on the line during configuration, set the PHYHOLD bit
to 1 in the EMACPC register.
2. Enable the clock to the PHY module by writing 0x0000.0001 to the Ethernet PHY Run Mode
Clock Gating Control (RCGCEPHY) register at offset 0x630 and then delay for 30 clock cycles
3. Enable power to the EPHY Module by writing 0x0000.0001 to the Ethernet PHY Run Mode
Clock Gating Control (RCGCEPHY) register at offset 0x69C.
4. Once the Ethernet PHY Peripheral Ready (PREPHY) register reads 0x0000.0001, software
can write the EMACPC register with the required value.
5. After software configuration is complete, the application must set the DONE bit in the Ethernet
PHY Configuration 1 (EPHYCFG1) register at offset 0x009.
Note: If a software reset is asserted to the PHY afterwards through the SREPHY register, the
custom configuration is lost and the steps described above must be repeated.
24.6 Register Map
Table 24-36 on page 1658 lists the Ethernet Controller MAC and PHY registers. For the MAC registers,
the offset listed is a hexadecimal increment to the MAC base address of 0x400E.C000. PHY registers
are accessed through the EMACMIIADDR register thus the base address is n/a (not applicable)
and noted as such above the register descriptions.
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY
layer. The registers are collectively known as the MII Management registers. Table 24-36 on page 1658
also lists these MII Management registers for interfacing to the internal PHY. All addresses given
are absolute and are written directly to the MII field of the Ethernet MAC MII Address
(EMACMIIADDR) register, offset 0x010. The PLA value of the EMACMIIADDR register for the
internal PHY is 0x00.
The Ethernet MAC MII Address (EMACMIIADDR) register, offset 0x010, is used to access MII
Management registers on the external PHY device. The PLA field in the EMACMIIADDR register
supports PHY addresses 1 to 31.
1657December 13, 2013
Texas Instruments-Advance Information
Tiva
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TM4C129XNCZAD Microcontroller