Datasheet

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The magic packet detection is updated in the EMACPMTCTLSTAT register for the received magic
packet. If the PMT interrupt is enabled in the Ethernet MAC Interrupt Mask (EMACIM) register, a
PMT interrupt is asserted and the EMACPMTCTLSTAT register can be read to determine whether
a magic packet frame has been received.
24.3.12.4 Power Management Interrupts
The PMT interrupt signal can be asserted when a valid remote wake-up frame or magic packet is
received. The PMT interrupt signal restores the application clock and TX clock to the MAC. When
the Ethernet MAC PMT Control and Status (EMACPMTCTLSTAT) register is read, the PMT
interrupt is cleared in the EMACRIS register at least after four clock cycles of RX clock. When
software resets the PWRDWN bit in the Ethernet MAC PMT Control and Status
(EMACPMTCTLSTAT) register, the MAC comes out of the power-down mode, but this event does
not generate at PMT interrupt.
24.3.12.5 Power-Down/Wake-Up Sequence
The recommended power-down and wake-up sequence is as follows:
1. Disable the Transmit DMA (if applicable) and wait for any previous frame transmissions to
complete. These transmissions can be detected when TI is set in the Ethernet MAC DMA
Interrupt Status (EMACDMARIS) register.
2. Disable the MAC transmit and receive state machine by clearing the TE and RE bits in the
Ethernet MAC Configuration (EMACCFG) register.
3. Wait until the RX DMA empties all the frames from the Rx FIFO to system memory by polling
the RXF field of the Ethernet MAC Status (EMACSTATUS) register.
4. Enable a power management mode by setting the magic packet, global unicast or remote
wake-up enable bit in the EMACPMTCTLSTAT register.
5. Enable the MAC receive state machine in the EMACCFG register and enter the Power-Down
mode by setting the PWRDWN bit in the EMACPMTCTLSTAT register.
6. On receiving a valid remote wake-up frame, the PMT interrupt is set in the EMACRIS register
and the Ethernet MAC exits the Power-Down mode.
7. Read the EMACPMTCTLSTAT register to clear the PMT interrupt, then enable the other modules
in the system and resume normal operation.
24.3.13 Serial Management Interface
The Ethernet MAC has the ability to read or write to the PHY registers through the EN0MDIO and
EN0MDC signals of the Serial Management Interface defined by the IEEE 802.3 standard. The
internal EN0MDIO and EN0MDC signals connect to the integrated PHY as well as to the external
EN0MDIO and EN0MDC pins. The EN0MDC signal is a 2.5 MHz clock that is sourced from System
Clock (SYSCLK) and then divided down to the required frequency by programming the CR field in
the Ethernet MAC MII Address (EMACMIIADDR) register. To access the integrated PHY, the PLA
field in the EMACMIIADDR register must be 0x0. The available addresses for external PHYs are
0x01 to 1F.
December 13, 20131646
Texas Instruments-Advance Information
Ethernet Controller