Datasheet

■ For IPv4 datagrams:
– The received Ethernet type is 0x0800, but the IP header's Version field is not equal to 0x4.
– The IPv4 Header Length field indicates a value less than 0x5 (20 bytes).
– The total frame length is less than the value given in the IPv4 Header Length field.
■ For IPv6 datagrams:
– The Ethernet type is 0x86dd but the IP header Version field is not equal to 0x6.
– The frame ends before the IPv6 header (40 bytes) or extension header (as given in the
corresponding Header Length field in an extension header) is completely received.
If the checksum offload engine detects an IP header error, it still inserts an IPv4 header checksum
if the Ethernet Type field indicates an IPv4 payload.
24.3.11 MAC Management Counters
The MAC Management Counters (MMC) module maintains a set of registers for gathering statistics
on the received and transmitted frames. The register set includes a control register for controlling
the behavior of the registers, two 32-bit registers containing interrupts generated (one for receive
and one for transmit), and two 32-bit registers containing masks for the Interrupt register (one for
receive and one for transmit).The MMC counters are free running and start counting when a
corresponding frame is received or transmitted. The MMC counter registers provided are as follows:
■ Ethernet MAC Transmit Frame Count for Good and Bad Frames (EMACTXCNTGB)
■ Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision
(EMACTXCNTSCOL)
■ Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions
(EMACTXCNTMCOL)
■ Ethernet MAC Transmit Octet Count Good (EMACTXOCTCNTG)
■ Ethernet MAC Receive Frame Count for Good and Bad Frames (EMACRXCNTGB)
■ Ethernet MAC Receive Frame Count for CRC Error Frames (EMACRXCNTCRCERR)
■ Ethernet MAC Receive Frame Count for Alignment Error Frames (EMACRXCNTALGNERR)
■ Ethernet MAC Receive Frame Count for Good Unicast Frames (EMACRXCNTGUNI)
24.3.12 Power Management Module
The power management (PMT) module supports the reception of network remote wake-up frames
and AMD Magic Packet™ frames. The PMT module does not perform the clock gate function, but
generates interrupts for remote wake-up frames and magic packets that the MAC receives.
When the application enables the power-down mode in the PMT module by setting the PWRDWN bit
in the Ethernet MAC PMT Control and Status Register (EMACPMTCTLSTAT) register, MAC
offset 0x02C, the MAC drops all received frames and does not forward any frame to the TX/RX
Controller RxFIFO or the application. The MAC comes out of the power-down mode only when a
magic packet or a remote wake-up frame is received and the corresponding detection is enabled.
1643December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller