Datasheet

24.3.7.3 Receive Timestamping
The MAC captures the timestamp of all received frames. The MAC does not process the received
frames to identify the PTP frames in default timestamping mode (when Advanced Timestamp is
disabled). The MAC gives the timestamp and the corresponding status to the TX/RX Controller
along with the EOF data. The TX/RX Controller validates and indicates the availability of the
timestamp so that the DMA can return the timestamp to the corresponding receive descriptor. The
64-bit timestamp information is written to the RDES2 and RDES3 fields. The timestamp is written
only to the receive descriptor for which the Last Descriptor status field has been set to 1 (the EOF
marker). When the timestamp is not available (for example, because of an RX FIFO overflow), an
all '1s' pattern is written to the descriptors (RDES2 and RDES3), indicating that the timestamp is
not correct. If timestamping is disabled, the DMA does not alter RDES2 or RDES3.
Note: When the enhanced descriptor size is selected by setting the ATDS bit in the
EMACDMABUSMOD register, the 64-bit timestamp is written to RDES6 and RDES7,
respectively. RDES0[7] indicates whether the timestamp is updated in RDES6 and RDES7.
24.3.7.4 Timestamp Error Margin
According to the IEEE 1588 specifications, a timestamp must be captured at the SFD of the
transmitted and received frames at the MAC interface. Because the reference timing source, MOSC,
is taken as different from MAC reference clocks, a small error margin is introduced, because of the
transfer of information across asynchronous clock domains. In the transmit path, the captured and
reported timestamp has a maximum error margin of 2 PTP (MOSC) clocks. It means that the captured
timestamp has the reference timing source (MOSC) value that is given within 2 clocks after the SFD
has been transmitted to the PHY. Similarly, in the receive path, the error margin is 3 MAC reference
clocks, plus up to 2 PTP clocks. The error margin of the three MAC reference clocks can be ignored
by assuming that this constant delay is present in the system (or link) before the SFD data reaches
the interface of MAC.
Note: When the Ethernet Controller is configured to use the MII interface to an external PHY, the
MII clock is provided by the external PHY through EN0RXCK and EN0TXCK. When the
Ethernet Controller is connected to the integrated PHY, the reference clock must be 25
MHz because it is also the source to the PHY.
Note: When IEEE 1588 timestamping is enabled with internal timestamp, use a PTP clock
frequency that is greater than 5 MHz. This is because the SSINC field in the
EMACSUBSECINC register limits the PTP frequency that can be used to ~4 MHz.
24.3.7.5 IEEE 1588-2008 Advanced Timestamps
In addition to the basic timestamp features mentioned in IEEE 1588-2002 Timestamps, the Ethernet
Controller supports the following advanced timestamp features defined in the IEEE 1588-2008
standard:
■ Supports the IEEE 1588-2008 (version 2) timestamp format.
■ Provides an option to take snapshot of all frames or only PTP type frames.
■ Provides an option to take snapshot of only event messages.
■ Provides an option to take the snapshot based on the clock type: ordinary, boundary, end-to-end,
and peer-to-peer.
■ Provides an option to select the node to be a master or slave clock.
1635December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller