Datasheet

3. Data can be sent to the TX/RX Controller in cut-through mode or store-and-forward mode. When
the RTC bit field of the EMACDMAOPMODE register is set to 0x0 and cut-through mode is
enabled (RSF=0), the TX/RX Controller indicates availability to transfer to the DMA when 64
bytes are in the RX FIFO or a full packet of data has been received into the RX FIFO. When
the DMA initiates transfers to system memory, the TX/RX Controller continues to transfer data
from the RX FIFO until a complete packet has been transferred. When EOF has occurred, the
TX/RX Controller sends the status word to the DMA.
Note: The timestamp transfer takes two clock cycles and the lower 32-bits of the timestamp
are sent first when timestamping is enabled.
When the RSF bit is set in the EMACDMAOPMODE register, RX FIFO store-and-forward mode
is enabled and a frame is read by the DMA only after it is completely written into the RX FIFO.
In this mode, only valid frames are read and forwarded to the application. In cut-through mode,
some error frames are not dropped because the error status is received at the end of the frame
and by that time the start of that frame has already been read out of the RX FIFO.
The TX/RX Controller is capable of storing any number of frames in the RX FIFO as long as it is
not full.
Error Handling
If the RX FIFO is full before it receives the EOF data from the MAC, an overflow is declared, the
entire frame (including the status word) is dropped and the Ethernet MAC Missed Frame and
Buffer Overflow Counter (EMACMFBOC) register is incremented. These error actions occur even
if the FEF bit is set in the EMACDMAPOPMODE register. If the start address of such a frame has
already been transferred to the TX/RX Controller, the rest of the frame is dropped and a dummy
EOF is written to the FIFO along with its status word. The descriptor status indicates a partial frame
because of overflow. In such frames, the Frame Length (FL) field in the receive descriptor is invalid.
If the RX FIFO is configured to operate in the store-and-forward mode and if the length of the received
frame is more than the FIFO size, overflow occurs and all such frames are dropped. During error
handling, the DMA flushes the error frame currently being read.
The Receive control logic can filter error and undersized frames if enabled through configuring the
FEF or FUF bit of the EMACDMAOPMODE register. Filtering must be set before the start address
of the frame has been transferred to the TX/RX controller for it to take effect.
Receive Word Status
At the end of an Ethernet frame transfer to the system memory, the TX/RX Controller sends a receive
status word, RDES0, to the application. Until the end of the frame transfer, the TX/RX Controller
stores the status and frame length in an asynchronous status FIFO whose depth is determined by
the size of the RX FIFO (2K) and the minimum size of the frame. If the frame size if 64, then the
asynchronous FIFO depth is 2048/64 = 32 bytes in length. Note that when the status of a partial
frame (because of overflow) is sent to the application, the Frame Length field of RDES0 is not valid
and is set to zero.
Note: When the timestamp feature is enabled, the receive status field is greater than 32-bits. An
extended status bit-field [63:32] provides information about the received Ethernet payload
when it is carrying PTP packets or TCP/UDP/ICMP over IP packets. Since the data bus is
32 bits, the status is transferred over two clock cycles.
1627December 13, 2013
Texas Instruments-Advance Information
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TM4C129XNCZAD Microcontroller