Datasheet

After more than 96 bytes are transferred to the MAC, the FIFO controller clears space in the FIFO
and makes it available to the DMA to transfer more data. Retransmission is not possible after this
threshold is crossed or when the MAC indicates a late collision event.
When a frame transmission is aborted because of underflow and a collision event follows, which
initiates a retry, then the retry has higher priority than the abort.
TX FIFO Flush Operation
The TX FIFO can be flushed by setting the FTF bit in the EMACDMAOPMODE register. The flush
operation is immediate and the TX/RX Controller clears the TX FIFO and the corresponding pointers
to the initial state even if it is in the middle of transferring a frame to the MAC. The data which is
already accepted by the MAC transmitter is not flushed. This data is scheduled for transmission
and results in an underflow event because the TX FIFO did not complete the transfer or the rest of
the frame. As in all underflow conditions, a runt frame is transmitted and observed on the line. The
status of such a frame is marked with both underflow and frame flush events in the Transmit
Descriptor 0 (TDES0) word.
The TX/RX Controller also stops accepting any data from the DMA during the flush operation. It
generates and transfers Transmit Status Words to the application for the frames that are flushed
inside the FIFO, including partial frames. Frames that are completely flushed in the TX/RX Controller
are identified by setting the Flush Status (FF) bit in the Transmit Descriptor 0 (TDES0) word. The
TX/RX Controller completes the flush operation when the DMA accepts all of the status words for
the frames that were flushed and then clears the TX FIFO Flush control (FTF) bit in the
EMACDMAOPMODE register. At this point, the TX/RX Controller starts accepting new frames from
the DMA.
Transmit Status Word
At the end of the transfer of the Ethernet frame to the MAC and after the MAC completes the
transmission of the frame, the TX/RX delivers a transmit status word (TDES0) to the application. If
IEEE timestamping is enabled, the TX/RX Controller returns the specific frame's 64-bit timestamp,
along with the transmit status word. The fields for the Transmit Descriptors are described in
“Descriptors” on page 1605.
24.3.5.2 Receive (RX) Control Path
TX/RX Controller receives frames from the MAC and pushes them into the RX FIFO. When the fill
level of the RX FIFO crosses the programmed RX Threshold, the DMA is notified.
Receive Operation
During a receive operation the TX/RX Controller is a slave to the MAC. The steps of the receive
operation are as follows:
1. The MAC receives a frame. This data, along with SOF, EOF and byte enable information is sent
to the TX/RX Controller. The TX/RX Controller accepts the data and pushes it into the RX FIFO.
After the EOF is transferred, the MAC drives the status word, which is also pushed in to the RX
FIFO.
2. When timestamp is enabled by setting the TSEN bit in the Ethernet MAC Timestamp Control
(EMACTIMSTCTRL) register, at offset 0x700, and the 64-bit timestamp is present with the
receive status, it is appended to the frame and received by the MAC and pushed into the TX
FIFO before the corresponding receive status word is written. Thus, two additional locations
per frame are taken for storing timestamp in the RX FIFO.
December 13, 20131626
Texas Instruments-Advance Information
Ethernet Controller